Transfer of large numbers of signals from a first logic block operating at a first rate to a second logic block operating at a second rate is presently limited by employing a form of synchronizing delay inserted between the logic blocks for each signal. Although the use of Large Scale Integration (LSI) and Very Large Scale Integration (VLSI) allows millions of logic circuits to be implemented within a small area within a silicon wafer, inserting large numbers of synchronizing delays consumes power, reduces the available circuit area on a wafer, and creates problems associated with timing and layout of the signals between the logic blocks. Further, increasing the amount of logic increases the amount of error reports generated during the design phase of the integrated circuit.
By way of example, the aforementioned problem is encountered with the implementation of video decoders and video on-screen display devices which typically process encoded video signals in the 33.75 MHz clock domain, but must format and supply digital video signals to display devices in the 27 MHz clock domain according to, for example, an NTSC standard. For these systems, the clock rates of the first and second logic blocks differ by no more than the frequency of the lower one of the two clock rates. Synchronizing delays are typically implemented by double latching each data signal provided from the first logic block with a first clock rate with a clock signal from the receiving logic block having a second clock rate.
FIG. 1 is a block diagram illustrating two interconnected logic blocks operating with different rates in a video decoder 110 of the prior art. Referring to FIG. 1, the video decoder includes a memory controller 111 which provides stored decoded digital video data for display. As shown, the memory controller 111 includes a high speed memory processing and storage unit 112 (shown as shaded section) which may operate at a 33.75 MHz rate, and a display interface 113 which controls the transfer of display information from memory to a display formatting section 114. The display interface 113 operates at a different rate, such as 27 MHz. As shown, the logic within the display formatting section also operates in the 27 MHz domain; consequently, each of the data signals transferred from the high speed memory processing and storage unit 112 at the higher data rate must be re-clocked and synchronized to a lower data rate. Similarly, data signals transferred from the lower data rate to the higher data rate must also be re-clocked and synchronized. In addition, set up registers 115 used by the memory controller 111 must include logic operating at both data rates. Once the data is processed and formatted as display data, it is provided to an external display device 314.
FIG. 2A is a block diagram illustrating a dual flip-flop configuration of the prior art employed to synchronize signals transferred between a first logic block operating at a first rate and a second logic block operating at a second rate. The configuration of FIG. 2A is used to transfer data having the lower rate to the logic operating at the higher rate. The synchronizing delay includes a first flip-flop 201 and second flip-flop 202. The data signal at the first rate to be transferred is provided to the first flip-flop 201, and the data value(s) latched into flip-flop 201 by a clock signal of the receiving block clock (not shown) at the second rate. These data values latched in flip-flop 201 are provided to and latched into the second flip-flop 202 by a second clock pulse at the second rate while the next data value is latched into the first flip flop 201. Consequently, two data values, which may be eight bit values, corresponding to a high and low byte, are buffered and available to the receiving block.
The configuration of FIG. 2A may also be used to transfer data having a higher rate to the logic operating at the lower rate, but the data at the higher rate must first be slowed down to a rate slower than the lower rate clock. Consequently, the clock rate of the data to be transferred is first divided by two before being provided to the first flip-flop 201.
FIG. 2B is a timing diagram illustrating the synchronization of a lower rate data signal having clock CLK2 including data values D1L and D2L provided to a higher rate logic block according to a double latching synchronizing delay of the prior art. The output data values D1H and D2H of the second flip flop of FIG. 2A are synchronized with the higher rate clock signal of the second logic block CLK1. However, because of the large number of different data signals which are transferred to and from the memory controller 111, many such synchronizing delays are required.
As is apparent from the above, there is a continuing need for an efficient and cost-effective method and system to synchronize large groups of signals transferred from a first logic block operating at a first rate to a second logic block operating at a second rate.